This invention relates in general to digital computational circuits and in particular, to an unsigned integer multiply/divide circuit with related control logic.
Several methods are well known for implementing integer multiply and divide circuits. Typically, these methods utilize operational algorithms in conjunction with components such as shift registers and adder circuits. See, e.g., Mano, M. M., Computer System Architecture, 2d Ed., Prentice/Hall, 1982.
Also, several methods are well known for implementing adder circuits. Two such methods are carry lookahead and carry selection. See, e.g., Hwang, K., Computer Arithmetic, John Wiley & Sons, Inc., 1979.
In integrated circuit implementations, increasing speed and reducing the number of transistors to accomplish the same function are highly desirable goals to improve device performance and reduce overall circuit size and, as a result, circuit cost. Therefore, it is a primary object of the present invention to provide an unsigned integer multiply/divide circuit that operates with improved speed characteristics and reduces the amount of integrated circuit area necessary for its implementation.